Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

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Date 12/14/2020
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1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes x
1.1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v20.4 1.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v18.0 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v17.1 1.4. Intel® Arria® 10 Hard IP for PCI Express* IP Core v17.0 1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1 1.6. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.0 1.7. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.1 1.8. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.0 1.9. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.1 1.10. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.0 Intel® Arria® 10 Edition 1.11. Intel® Arria® 10 Hard IP for PCI Express* IP Core v13.1 Arria 10 Edition
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

1.7. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.1

Table 7.  15.1 November 2015
Description Impact
Added Example Designs tab that automatically generates both simulation and hardware example designs with the parameters you specify. You can now download an example design to the Altera Arria 10 GX FPGA Development Kit using only the automatically generated files.
Revised the component GUI. For example, is a new single parameter, HIP mode combines all supported data rates, interface widths and frequencies as a single parameter. Improves usability of the component GUI.
Added support for optional Avalon-ST clr_st reset output port which has the same functionality as the reset_status in the hip_rst conduit interface. This signal eliminates Avalon Streaming reset warnings.
Increased the number of tags supported to 256 from 64 for the Avalon-MM with DMA interface. Enhances DMA throughput for high latency systems.
Added support for RX Completion buffer overflow monitoring. Improves system visibility, resulting in better optimization of RX buffer.
Added preliminary support for Gen3 x4, Gen3 x8, and Gen2 x8 Root Port when you select the 256-bit Avalon-MM interface. Extends Avalon-MM Root Port support to include 64-, 128-, and 256-bit interfaces.
Replaced the SR-IOV DMA example design with a target example design that includes 1 physical function and 3 virtual functions. This design provides a simpler introduction to the SR-IOV functionality.
Added support for immediate writes when you select the Avalon-MM with DMA interface. Provides an efficient mechanism for writing a single dword of data.
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