Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

ID 683487
Date 12/14/2020
Public

1.8. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.0

Table 8.  15.0 May 2015
Description Impact
Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY register programming with the Altera System Console. If you turn on this option, you can use the Altera System Console for enhanced debugging.
In IP core variations with the Avalon-MM DMA interface, added support for downstream burst read request for a payload of size up to 4 KBytes, if Enable burst capability for RXM BAR2 port is turned on in the Parameter Editor. Previous maximum downstream read request payload size was 512 bytes. If you choose the Avalon-MM DMA interface, the IP core can receive and process a burst read request for a payload of any size supported by the PCI Express specification (up to 4 KBytes), if it receives such a burst read request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to send message TLPs with data payload of any length from a Root Port. If you choose the Avalon-MM interface, a Root Port IP core can send messages with payload greater than 1 dword.
In IP core variations with the Avalon-MM interface, added support for dynamically generated Platform Designer example designs that reflect the parameters that you selected in the Parameter Editor. This feature was new in the IP core v14.1 with the Avalon-ST interface, and is now provided also with the Avalon-MM interface. If you choose the Avalon-MM interface and click the Example Design button, the Quartus II software generates an example design that matches the current parameter settings, for most IP core variations,
In IP core variations with the Avalon-MM or Avalon-MM DMA interface, added Enable Hard IP Status Bus when using the AVMM interface parameter. This parameter makes visible or hides the link status signals, ECC error signals, TX and RX parity error signals, completion header and data signals, and currentspeed signal. Refer to the Arria 10 HIP for PCI Express Signal Changes v15.0 table.
The IP core no longer generates with a Synopsys Design Constraints file (.sdc) that includes a derive_pll_clocks constraint. Instead, in compliance with Arria 10 design requirements, the user must add the timing constraint macro derive_pll_clocks -create_base_clocks to a top-level .sdc file. User must add this constraint in a top-level Synopsys Design Constraints file. This constraint was previously included in the IP core SDC file.
Table 9.  Arria 10 HIP for PCI Express Signal Changes v15.0Signals added or modified in version 15.0.
Signal Name New Behavior
derr_cor_ext_rcv The presence or absence of these signals is now controlled by the new Enable Hard IP Status Bus when using the AVMM interface parameter. If the parameter is turned on, the signals are included. If the parameter is turned off, the signals are not available.
derr_cor_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
l2_exit
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err[1:0]
cfg_par_err
ko_cpl_spc_header[7:0]
ko_cpl_spc_data[11:0]
currentspeed[1:0]

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