Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

ID 683487
Date 12/14/2020
Public

1.9. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.1

Table 10.  14.1 December 2014
Description Impact
Reduced Quartus II compilation warnings by 50%. Reduces time required to vet compilation warnings.
Added support for Single-Root I/O Virtualization (SR-IOV) interface. If you choose to use the SR-IOV interface, you need to redesign your Application Layer.
Added support for dynamically generated Platform Designer example designs that reflects the parameters that you selected in the Parameter Editor. If you choose the Avalon-ST interface, the automatically generated testbench has the parameters that you specified.
Added support for Configuration Space Bypass Mode when using the Avalon-ST interface. If you choose to use Configuration Space Bypass Mode, you need to redesign your Application Layer.
Added Quartus II compilation support for the Avalon-MM with DMA interface. You can now compile for the Avalon-MM with DMA interface and download the Programmer Object File .pof to a development board.
The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade but does not clarify the reason. If you generate your IP core outside a Quartus II project, you must ensure that you specify a device for your Arria 10 IP core variation and regenerate it in the Quartus II software v14.1.

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