1.10. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.0 Intel® Arria® 10 Edition
|Changed the PIPE interface to 32 bits for all data rates.||This change requires you to recompile your v13.1 variant in 14.0a10 release|
|Added simulation log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory. Generation of the log file requires the following simulation file, <install_dir>altera/altera_pcie/altera_pcie_a10_hip/altpcie_monitor_a10_dlhip_sim.sv, that was not present in earlier releases of the Quartus II software.|
|Added option to enable 62.5 MHz application clock for Gen1 x1 data rate.||If you choose this option, you must regenerate your IP core.|
|Added third interface option, Avalon-MM with DMA, that includes a high performance DMA. If you choose this option, you must regenerate your IP core.|
|Added option to integrate the Descriptor Controller in the variant for the Avalon-MM with DMA interface.||-|
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