AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

ID 683478
Date 12/18/2015
Public

1.3.1.2. Initial Frame and Lane Synchronization

Table 2.  Initial Frame and Lane Synchronization Test Cases

Test Case

Objective

Description

Passing Criteria

ILA.1

Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe.

Verify that four multiframes are transmitted in ILAS phase and the receiver detects the initial lane alignment sequence correctly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by a 32-bit data bus in the jesd204_tx_pcs_datasignal. The 32-bit data bus is divided into 4 octets.

Check the following errors in the AD9144 registers:

  • Frame Synchronization
  • Initial Lane Synchronization
  • The /R/ character or K28.0 (0x1C) is transmitted at the jesd204_tx_pcs_data bus to mark the beginning of multiframe.
  • The /A/ character or K28.3 (0x7C) is transmitted at the jesd204_tx_pcs_data bus to mark the end of each multiframe.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are transmitted.
  • The “Frame and Initial Lane Synchronization” status for all lanes are asserted in the AD9144 registers 0x471 and 0x473 respectively.

ILA.2

Check that the JESD204B configuration parameters are transmitted in the second multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0] 2

The following signal in <ip_variant_name>.v is tapped:

  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the following registers:

  • ilas_data1
  • ilas_data2

The content of 14 configuration octets in the second multiframe is stored in the above 32-bit registers.

Check the following error in the AD9144 register:

  • Configuration Mismatch Error
  • The /R/ character is followed by /Q/ character or K28.4 (0x9C) in the jesd204_tx_pcs_data signal at the beginning of the second multiframe.
  • The jesd204_tx_int is deasserted if there is no error.
  • The JESD204B parameters read from ilas_data1 and ilas_data2 registers are the same as the parameters set in the JESD204B IP core Qsys parameter editor.
  • The “Link Configuration Mismatch Error” bit n the AD9144 register 0x47B is not asserted.

ILA.3

Check the constant pattern of transmitted user data after the end of the 4th multiframes.

Verify that the receiver successfully enters user data phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0] 2

The following signal in <ip_variant_name>.v is tapped:

  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the tx_err register.

Check the following errors in the AD9144 register:

  • Lane FIFO Full
  • Lane FIFO Empty
  • When scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the 4th multiframe transmitted. 3
  • Bits 2 and 3 of the tx_err register are not set to “1”.
  • The “Lane FIFO Full” and “Lane FIFO Empty” in the AD9144 registers 0x30C and 0x30D are not asserted.
  • The jesd204_tx_int is deasserted if there is no error.
2 L denotes the number of lanes.
3 When the scrambler is turned on, the data pattern cannot be recognized after the 4th multiframe in the ILAS phase.

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