AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

ID 683478
Date 12/18/2015
Public

1.3.1.1. Code Group Synchronization (CGS)

Table 1.  CGS Test Cases

Test Case

Objective

Description

Passing Criteria

CGS.1

Check that /K/ characters are transmitted when sync_n signal is asserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II .

Each lane is represented by a 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the following error in the AD9144 register:

  • Code Group Synchronization Status
  • /K/ character or K28.5 (0xBC) is transmitted at each octet of the jesd204_tx_pcs_data bus when the receiver asserts the sync_n signal.
  • The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters like /K/ are transmitted.
  • The jesd204_tx_int signal is deasserted if there is no error.
  • The “Code Group Synchronization Status” for all lanes should be asserted in AD9144 register 0x470.

CGS.2

Check that /K/ characters are transmitted after sync_n is deasserted but before the start of multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • tx_sysref
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II .

Each lane is represented by a 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the following error in the AD9144 register:

  • 8b/10b Not-in-Table Error
  • 8b/10b Disparity Error
  • The /K/ character transmission continues for at least 1 frame plus 9 octets.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • The “8b/10b Not-in-Table Error” and “8b/10b Disparity Error” bit in the AD9144 registers 0x46E and 0x46D are not asserted.
1 L denotes the number of lanes.

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