AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

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ID 683478
Date 12/18/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9144 Configurations 1.5. Test Results 1.6. Test Results Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

1.5. Test Results

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7.  Test Results

Test

L

M

F

Subclass

SCR

K

Lane rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Results

1

8

4

1

1

0

32

9830.4

983.04

245.76

PASS with comments

2

8

4

1

1

1

32

9830.4

983.04

245.76

PASS with comments

3

8

4

2

1

0

16

9830.4

983.04

245.76

PASS with comments

4

8

4

2

1

1

16

9830.4

983.04

245.76

PASS with comments

5

8

4

2

1

0

32

9830.4

983.04

245.76

PASS with comments

6

8

4

2

1

1

32

9830.4

983.04

245.76

PASS with comments

7

4

4

2

1

0

16

9830.4

491.52

245.76

PASS

8

4

4

2

1

1

16

9830.4

491.52

245.76

PASS

9

4

4

2

1

0

32

9830.4

491.52

245.76

PASS

10

4

4

2

1

1

32

9830.4

491.52

245.76

PASS

11

2

4

4

1

0

16

9830.4

245.76

245.76

PASS

12

2

4

4

1

1

16

9830.4

245.76

245.76

PASS

13

2

4

4

1

0

32

9830.4

245.76

245.76

PASS

14

2

4

4

1

1

32

9830.4

245.76

245.76

PASS

15

4

2

1

1

0

32

9830.4

983.04

245.76

PASS

16

4

2

1

1

1

32

9830.4

983.04

245.76

PASS

17

4

2

2

1

0

16

9830.4

983.04

245.76

PASS

18

4

2

2

1

1

16

9830.4

983.04

245.76

PASS

19

4

2

2

1

0

32

9830.4

983.04

245.76

PASS

20

4

2

2

1

1

32

9830.4

983.04

245.76

PASS

21

2

2

2

1

0

16

9830.4

491.52

245.76

PASS

22

2

2

2

1

1

16

9830.4

491.52

245.76

PASS

23

2

2

2

1

0

32

9830.4

491.52

245.76

PASS

24

2

2

2

1

1

32

9830.4

491.52

245.76

PASS

25

1

2

4

1

0

16

9830.4

245.76

245.76

PASS

26

1

2

4

1

1

16

9830.4

245.76

245.76

PASS

27

1

2

4

1

0

32

9830.4

245.76

245.76

PASS

28

1

2

4

1

1

32

9830.4

245.76

245.76

PASS

29

2

1

1

1

0

32

9830.4

983.04

245.76

PASS

30

2

1

1

1

1

32

9830.4

983.04

245.76

PASS

31

1

1

2

1

0

16

9830.4

491.52

245.76

PASS

32

1

1

2

1

1

16

9830.4

491.52

245.76

PASS

33

1

1

2

1

0

32

9830.4

491.52

245.76

PASS

34

1

1

2

1

1

32

9830.4

491.52

245.76

PASS
Figure 5. Sinewave Output from DAC Analog Channel
Table 8.  Deterministic Latency Test Results
Test L M F Subclass SCR K Lane rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) Allowed Deviation (ns)

Total Latency Result (ns)
1 8 4 1 1 1 32 9830.4 983.04 245.76 2.54 PASS with comments (206.6-208.9)
2 8 4 2 1 1 16 9830.4 983.04 245.76 2.54 PASS with comments (214.6-216.9)
3 8 4 2 1 1 32 9830.4 983.04 245.76 2.54 PASS with comments (209.9-212.2)
4 4 4 2 1 1 16 9830.4 491.52 245.76 3.05 PASS with comments (300.7-302.9)
5 4 4 2 1 1 32 9830.4 491.52 245.76 3.05 PASS with comments (300.8-303.1)
6 2 4 4 1 1 16 9830.4 245.76 245.76 4.07 PASS (483.6-483.8)
7 2 4 4 1 1 32 9830.4 245.76 245.76 4.07 PASS (479.3-479.6)
8 4 2 1 1 1 32 9830.4 983.04 245.76 2.54 PASS with comments (210.8-212.9)
9 4 2 2 1 1 16 9830.4 983.04 245.76 2.54 PASS with comments (208.2-210.5)
10 4 2 2 1 1 32 9830.4 983.04 245.76 2.54 PASS with comments (209.6-211.9)
11 2 2 2 1 1 16 9830.4 491.52 245.76 3.05 PASS with comments (300.8-303.1)
12 2 2 2 1 1 32 9830.4 491.52 245.76 3.05 PASS with comments (298.6-300.8)
13 1 2 4 1 1 16 9830.4 245.76 245.76 4.07 PASS (483.3-483.5)
14 1 2 4 1 1 32 9830.4 245.76 245.76 4.07 PASS (477.5-477.8)
15 2 1 1 1 1 32 9830.4 983.04 245.76 2.54 PASS with comments (208.0-210.2)
16 1 1 2 1 1 16 9830.4 491.52 245.76 3.05 PASS with comments (301.3-303.5)
17 1 1 2 1 1 32 9830.4 491.52 245.76 3.05 PASS with comments (297.3-300.0)
Figure 6. Time Difference Between Pulses in Deterministic Latency Measurement for LMF = 422 Configuration
Level Two Title