AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

ID 683478
Date 12/18/2015
Public

1.6. Test Results Comments

In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and until user data phase.

Data integrity is checked at the DAC datapath layer using the PRBS-7 pattern. The datapath PRBS can verify that the AD9144 datapath receives and correctly decodes the data. The datapath PRBS can also verify these processes:

  • the JESD204B parameters of the transmitter and receiver matched
  • the lanes of the receiver are mapped appropriately
  • the lanes have been appropriately inverted, if necessary
  • the start-up routine has been implemented correctly

Sinewave is observed at all four analog channels when sinewave generators in the FPGA are enabled. The data integrity test is also carried out for different link resets, where the PRBS checker is reinitialized and the status is checked. It is observed that if the LMFC Var and LMFC Del registers at the DAC side are not correctly configured, then it leads to random PRBS test failures. Hence, these registers are fine-tuned by reading registers DYN_LINK_LATENCY_x (DAC register 0x302 and 0x303). By repeatedly power-cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate LMFC Var and LMFC Del. For information on how to calculate these register values, refer AD9144 datasheet. Setting LMFC Del appropriately ensures that all the corresponding data samples arrive in the same LMFC period. Then, LMFC Var is written into the receive buffer delay (RBD) to absorb all link delay variation. This ensures that all data samples have arrived before reading. By setting these to fixed values across runs and devices, deterministic latency is achieved. The following table gives the calculated LMFC Var and LMFC Del for each mode. The same values are also programmed in the scripts corresponding to each mode.

S. No. L M F K Lane rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) LMFC Var LMFC Del
1 8 4 1 32 9830.4 983.04 245.76 0x6 0
2 8 4 2 16 9830.4 983.04 245.76 0x7 0
3 8 4 2 32 9830.4 983.04 245.76 0x7 0xE
4 4 4 2 16 9830.4 491.52 245.76 0x6 0
5 4 4 2 32 9830.4 491.52 245.76 0x7 0xC
6 2 4 4 16 9830.4 245.76 245.76 0x5 0x7
7 2 4 4 32 9830.4 245.76 245.76 0x6 0x16
8 4 2 1 32 9830.4 983.04 245.76 0x6 0x4
9 4 2 2 16 9830.4 983.04 245.76 0x7 0
10 4 2 2 32 9830.4 983.04 245.76 0x6 0x10
11 2 2 2 16 9830.4 491.52 245.76 0x6 0
12 2 2 2 32 9830.4 491.52 245.76 0x5 0x10
13 1 2 4 16 9830.4 245.76 245.76 0x5 0x7
14 1 2 4 32 9830.4 245.76 245.76 0x5 0x18
15 2 1 1 32 9830.4 983.04 245.76 0x6 0x4
16 1 1 2 16 9830.4 491.52 245.76 0x6 0
17 1 1 2 32 9830.4 491.52 245.76 0x4 0x12

Also, using normal equalization mode at the DAC to compensate for the insertion loss of up to 17.5 dB helps improve the data integrity test results. After these changes (LMFC registers and equalization), no data integrity issue is observed from the datapath layer of PRBS test at the DAC JESD core except in the modes LMF =841 and LMF=842. In these modes, the datapath PRBS fails, but very rarely. The PRBS test fails about 2-4 times out of 50 PRBS tests across different link resets. This behavior is not observed in any of the other modes. Hence these modes (LMF=841 & 842) are given a status of ‘PASS with comments’ in the test results table.

In deterministic latency test, there is consistent total latency across the JESD204B link and DAC analog channels. But in most of the LMF modes, about 2.2 ns mean variation in the DL is observed. For the latency to be deterministic, it is important that the SYSREF gets sampled at the same time at both the DAC and FPGA, and each SYSREF needs to be phase aligned at the same LMFC boundary.

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