AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

ID 683478
Date 12/18/2015
Public

1.3.3. Scrambling

With descrambler enabled, the transport layer test pattern checker at the DAC JESD core checks the data integrity of the scrambler in the FPGA.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 4.  Scrambler Test Cases

Test Case

Objective

Description

Passing Criteria

SCR.1

Check the functionality of the scrambler using PRBS test pattern.

Enable descrambler at the DAC and scrambler at the TX JESD204B IP core.

The signals that are tapped in this test case are similar to test case TL.1.

Check the following error in the AD9144 register:

  • PRBS Error
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The PRBS Error bit in the AD9144 registers 0x14C and 0x14D are deasserted.The jesd204_tx_int signal is also deasserted.
SCR.2 Verify the data transfer from digital to analog domain.

Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core.

Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.
A monotone sinewave is observed on the oscilloscope.

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