AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

ID 683477
Date 1/23/2018
Public

VCS

A file list template is included with the Avery simulation scripts (vcs/pcie_example_design_tb.f).

However, many file names are uniquely generated when you create the example design and they must be transferred to the example design file list, so you must add the file names yourself.

  1. In a text editor, open vcs/pcie_example_design_tb.f.
  2. Open <Example_Design_Directory>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs/vcs_setup.sh. This file contains a list of all design files that need to be compiled for simulation.
  3. Scroll through vcs_setup.sh until you locate the file list. The first file in this list should be altera_primitives.v and the last should be pcie_example_design_tb.v.
  4. Copy this list into the marked area of vcs/pcie_example_design_tb.f.
    Figure 4. Marked Area of vcs/pcie_example_design_tb.f
  5. Close vcs_setup.sh.
  6. Remove the trailing \ character from the end of every line in the copied file list of the pcie_example_design_tb.f.
  7. Remove the following final four files from the list:
    • altpcie_s10_tbed_hwtcl.v
    • altpcied_s10_hwtcl.sv
    • DUT_pcie_tb_ip.v
    • pcie_example_design_tb.v
    These files all instantiate the Intel FPGA root complex BFM and will be replaced by Avery files.
  8. In place of these files add $QSYS_SIMDIR/pcie_example_design_tb.sv. This is the new top-level file provided with the Avery simulation scripts that instantiates the Avery BFM.
  9. Save and close pcie_example_design_tb.f.
  10. In a text editor, open the Avery_sim_script/vcs/vcstest.sh.
  11. In line 8, specify your Intel® Quartus® Prime Pro Edition software installation path using QUARTUS_INSTALL_DIR environment variable. For example, export QUARTUS_INSTALL_DIR="/tools/acds/17.1/240/linux64/quartus".
  12. Save and close vcstest.sh.

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