AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

ID 683477
Date 1/23/2018
Public

Testbench Top-level File

Testbench top-level file modification is performed automatically, and a new top-level file (pcie_example_design_tb.sv) is included with the Avery simulation scripts.

It has the same name as the old top-level, but instantiates the Avery BFM in place of the Intel FPGA BFM. Additionally, the file format is changed from Verilog to System Verilog to facilitate integration with the Avery BFM.

For the VCS simulator, you should have added the new top-level to the file list in VCS. For the ModelSim simulator, the script, mentor.do, compiles the new top-level separately after compiling all other design files.

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