AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

ID 683477
Date 1/23/2018
Public

Download and Extract the Avery Simulation Scripts

  1. Download the Avery simulation scripts referenced below.
  2. Copy the Avery_sim_script.zip file to the <Example_Design_ Directory>/pcie_example_design_tb/pcie_example_design_tb directory.
  3. Navigate to the <Example_Design_ Directory>/pcie_example_design_tb/pcie_example_design_tb directory and unzip Avery_sim_script.zip.
Table 1.  Archive Contents
Archive Element Description
pcie_example_design_tb.sv This file is a replacement for the top-level simulation RTL file generated by the Intel® Quartus® Prime Pro Edition software. It removes the instantiation of the Intel FPGA root complex BFM, and adds the Avery root complex BFM. Additionally it changes the file format from Verilog to System Verilog, which is important for integrating with the Avery BFM in the VCS simulation.
apci_top_rc.sv This file is the top-level wrapper for the Avery root complex BFM.
vcs/ This folder contains:
  • A file-list of all Avery BFM files required by the VCS simulator (avery_files_vcs.f)
  • A file-list of all Intel® Quartus® Prime Pro Edition software-generated files required by the VCS simulator (pcie_example_design_tb.f)
  • A shell script to compile all necessary design files and run the simulation (vcstest.sh)
modelsim/ This folder contains:
  • A file-list of all Avery BFM files required by the ModelSim simulator (avery_files_ms.f)
  • A TCL simulation script with the procedures for simulation (msim_setup_avery.tcl)
  • A .do script to compile all necessary design files, elaborate, and run the simulation (mentor.do)

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