- Open modelsim/mentor.do in a text editor.
- Modify TOP_LEVEL_NAME to match your project. By default, an example design generated by Platform Designer will have a top level module name of pcie_example_design_tb.pcie_example_design_tb. Only modify this variable if you have changed the name of the top-level file.
- Modify QSYS_SIMDIR to match the path to your project’s simulation directory. This can be either an absolute path or a relative path. The default value assumes that you unzipped the Avery simulation files to the <Example_Design_Directory>/pcie_example_design_tb/pcie_example_design_tb directory. If you unzipped them elsewhere or made any other changes to the structure or naming of the project, then you must change this path.
- Modify AVERY_PCIE to match the path to the Avery BFM.
- Modify QUARTUS_INSTALL_DIR to match the path to your Intel® Quartus® Prime Pro Edition software installation.
- Modify AVERY_PLI to match the path to the Avery PLI library.
- Modify USER_DEFINED_ELAB_OPTIONS. By default, these options reference the PLI library and instruct elaboration to wait for an available Avery license. Modify this variable only if you need to make changes to these options.
- Modify USER_DEFINED_COMPILE_OPTIONS. By default, PIPE simulation is enabled. To enable serial simulation, append +define+APCI_NEW_PHY to the user compile options. For example, set the variable to "+define+APCI_DUMP_WLF+define+APCI_NEW_PHY".
Did you find the information on this page useful?