Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Managing Intel® Quartus® Prime Projects 4. Design Planning 5. Introduction to Intel® FPGA IP Cores 6. Migrating to Intel® Quartus® Prime Pro Edition 7. Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. FPGA Basic Design Prerequisites 2.2. Selecting an Intel® Quartus® Prime Software Edition 2.3. Introduction to Intel® Quartus® Prime Pro Edition Revision History
3. Managing Intel® Quartus® Prime Projects x
3.1. Creating a New FPGA Design Project 3.2. Viewing Basic Project Information 3.3. Intel® Quartus® Prime Project Contents 3.4. Managing Project Settings 3.5. Managing Logic Design Files 3.6. Managing Timing Constraints 3.7. Integrating Other EDA Tools 3.8. Exporting Compilation Results 3.9. Migrating Projects Across Operating Systems 3.10. Archiving Projects 3.11. Command-Line Interface 3.12. Managing Projects Revision History
3.1. Creating a New FPGA Design Project x
3.1.1. Using the Board-Aware Flow
3.1.1. Using the Board-Aware Flow x
3.1.1.1. Creating a New Project from a Design Example 3.1.1.2. Specifying a Target Board for the Project
3.1.1.1. Creating a New Project from a Design Example x
3.1.1.1.1. Family, Device & Board Settings 3.1.1.1.2. Accessing Pre-Installed Design Examples 3.1.1.1.3. Accessing Online Design Examples 3.1.1.1.4. Accessing Downloaded Design Examples
3.1.1.1.3. Accessing Online Design Examples x
3.1.1.1.3.1. Internet Connectivity Options 3.1.1.1.3.2. Design Examples Options
3.2. Viewing Basic Project Information x
3.2.1. Using the Compilation Dashboard 3.2.2. Viewing Project Reports 3.2.3. Viewing Project Messages
3.2.3. Viewing Project Messages x
3.2.3.1. Viewing Synthesis Warning Messages 3.2.3.2. Suppressing Message Display 3.2.3.3. Promoting Critical Warnings to Errors
3.3. Intel® Quartus® Prime Project Contents x
3.3.1. Project File Best Practices
3.4. Managing Project Settings x
3.4.1. Optimizing Project Settings
3.4.1. Optimizing Project Settings x
3.4.1.1. Optimize Settings with Design Space Explorer II 3.4.1.2. Optimize Settings with Project Revisions 3.4.1.3. Back-Annotate Optimized Assignments
3.5. Managing Logic Design Files x
3.5.1. Including Design Libraries 3.5.2. Creating a Project Copy
3.8. Exporting Compilation Results x
3.8.1. Exporting a Version-Compatible Compilation Database 3.8.2. Importing a Version-Compatible Compilation Database 3.8.3. Creating a Design Partition 3.8.4. Exporting a Design Partition 3.8.5. Reusing a Design Partition 3.8.6. Viewing Quartus Database File Information 3.8.7. Clearing Compilation Results
3.8.6. Viewing Quartus Database File Information x
3.8.6.1. QDB File Attribute Types
3.9. Migrating Projects Across Operating Systems x
3.9.1. Migrating Design Files and Libraries 3.9.2. Design Library Migration Guidelines
3.9.1. Migrating Design Files and Libraries x
3.9.1.1. Use Relative Paths
3.10. Archiving Projects x
3.10.1. Manually Adding Files To Archives 3.10.2. Archiving Projects for Service Requests 3.10.3. Archiving Projects for External Revision Control 3.10.4. Creating Database-Only Archives
3.10.3. Archiving Projects for External Revision Control x
3.10.3.1. Project Files to Include In External Revision Control
3.11. Command-Line Interface x
3.11.1. Project Revision Commands 3.11.2. Project Archive Commands 3.11.3. Project Database Commands
3.11.3. Project Database Commands x
3.11.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
4. Design Planning x
4.1. Design Planning 4.2. Create a Design Specification and Test Plan 4.3. Plan for the Target Device or Board 4.4. Plan for Intellectual Property Cores 4.5. Plan for Standard Interfaces 4.6. Plan for Device Programming 4.7. Plan for Device Power Consumption 4.8. Plan for Interface I/O Pins 4.9. Plan for other EDA Tools 4.10. Plan for On-Chip Debugging Tools 4.11. Plan HDL Coding Styles 4.12. Plan for Hierarchical and Team-Based Designs 4.13. Design Planning Revision History
4.3. Plan for the Target Device or Board x
4.3.1. Device Migration Planning
4.9. Plan for other EDA Tools x
4.9.1. Third-Party Synthesis Tools 4.9.2. Third-Party Simulation Tools
4.11. Plan HDL Coding Styles x
4.11.1. Design Recommendations 4.11.2. Recommended HDL Coding Styles 4.11.3. Managing Metastability
4.12. Plan for Hierarchical and Team-Based Designs x
4.12.1. Flat Compilation without Design Partitions
5. Introduction to Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Introduction to Intel FPGA IP Cores Revision History
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Migrating to Intel® Quartus® Prime Pro Edition x
6.1. Keep Pro Edition Project Files Separate 6.2. Upgrade Project Assignments and Constraints 6.3. Upgrade IP Cores and Platform Designer Systems 6.4. Upgrade Non-Compliant Design RTL 6.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
6.2. Upgrade Project Assignments and Constraints x
6.2.1. Modify Entity Name Assignments 6.2.2. Resolve Timing Constraint Entity Names 6.2.3. Verify Generated Node Name Assignments 6.2.4. Replace Logic Lock (Standard) Regions 6.2.5. Modify Signal Tap Logic Analyzer Files 6.2.6. Remove References to .qip Files 6.2.7. Remove Unsupported Feature Assignments
6.2.4. Replace Logic Lock (Standard) Regions x
6.2.4.1. Logic Lock Region Assignment Examples
6.4. Upgrade Non-Compliant Design RTL x
6.4.1. Verify Verilog Compilation Unit 6.4.2. Update Entity Auto-Discovery 6.4.3. Ensure Distinct VHDL Namespace for Each Library 6.4.4. Remove Unsupported Parameter Passing 6.4.5. Remove Unsized Constant from WYSIWYG Instantiation 6.4.6. Remove Non-Standard Pragmas 6.4.7. Declare Objects Before Initial Values 6.4.8. Confine SystemVerilog Features to SystemVerilog Files 6.4.9. Avoid Assignment Mixing in Always Blocks 6.4.10. Avoid Unconnected, Non-Existent Ports 6.4.11. Avoid Illegal Parameter Ranges 6.4.12. Update Verilog HDL and VHDL Type Mapping
6.4.1. Verify Verilog Compilation Unit x
6.4.1.1. Verilog HDL Configuration Instantiation
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Managing Intel® Quartus® Prime Projects
4. Design Planning
5. Introduction to Intel® FPGA IP Cores
6. Migrating to Intel® Quartus® Prime Pro Edition
7. Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

3.1.1.1. Creating a New Project from a Design Example

The Intel® Quartus® Prime software provides access to installed and online platform- and board-specific design examples that you can use as a starting point for your own design. You can accelerate your design progress by starting from a pre-validated design example that installs with the Intel® Quartus® Prime software or is available online.

This technique can be especially helpful if you are new to FPGA design or EDA design tools. The design example can help you to quickly analyze a validated design on a board and appropriately configure it in various ways to match your users’ needs. Alternatively, you can start with an Empty Project for which you specify all settings and design files.

  • Pre-installed design examples—you can immediately access the design examples that install along with the Intel® Quartus® Prime software installation at: <quartus>\acds\quartus\common\board_designs.
  • Online design examples—you can access design examples hosted online, which includes designs from the Intel FPGA Design Store.
  • Downloaded design examples—you can access your previously downloaded design examples, or any design example that you store in a local drive, under downloaded reference designs.

To create a new Intel® Quartus® Prime project that is based on a design example, follow these steps:

  1. the Intel® Quartus® Prime software, click File > New Project Wizard. Click Next to view the Family, Device & Board Settings wizard page.
  2. Under the Select the type of project to create, select Design Example and click Next. The Family, Device & Board Settings page appears, allowing you to find and select the design example from which to base your project.
    Figure 4. Family, Device & Board Settings Page of New Project Wizard


  3. Under What is the working directory for this project?, specify the directory to store your project files and click Next.
  4. Under Find Options, select the Family, Development Kit, and Vendor design example you want to use. Refer to Family, Device & Board Settings.
    Figure 5. Board Tab in New Project Wizard


    The search results display the design examples that meet your search criteria.

  5. Select the design example that you want in the search results and click Next. If the design example is licensed by Intel FPGA, a Software License Agreement page appears that prompts you to accept the license agreement before you can proceed.
  6. Click Next to proceed to the Summary page.
  7. Click Finish to deploy the selected design example in the Intel® Quartus® Prime software. When a design example downloads, the design's .par downloads to the download path that you define in More Settings, but the design itself extracts to the project working directory that you specify.
Also refer to Accessing Online Design Examples and Accessing Downloaded Design Examples.

Section Content
Family, Device & Board Settings
Accessing Pre-Installed Design Examples
Accessing Online Design Examples
Accessing Downloaded Design Examples

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