2.2. Selecting an Intel® Quartus® Prime Software Edition
- Select the Intel® Quartus® Prime Pro Edition software if you are beginning a new Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10 or Intel® Agilex™ design, or to take advantage of the unique features of Intel® Quartus® Prime Pro Edition.
- Select the Intel® Quartus® Prime Standard Edition software if your design must target Arria® V, Arria® , Intel® Cyclone® 10 LP, Cyclone IV, Cyclone V, or MAX® series devices, and you do not want to migrate you design to a device that Intel® Quartus® Prime Pro Edition supports.
The following features are only available in the Intel® Quartus® Prime Pro Edition software:
- Hyper-Aware Design Flow—use Hyper-Retiming to reach the highest performance in Intel® Agilex™ and Intel® Stratix® 10 devices.
- Advanced synthesis—integrates new, stricter language parser supporting all major IEEE RTL languages, with enhanced algorithms, and parallel synthesis capabilities, and support for SystemVerilog 2009.
- Hierarchical project structure—preserve individual post-synthesis, post-placement, and post-place and route results for design instances. Optimizes without impacting other partition placement or routing.
- Incremental Fitter Optimizations—run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports.
- Faster, more accurate I/O placement—plan interface I/O in Interface Planner.
- Platform Designer (Pro)—builds on the system design and custom IP integration capabilities of Platform Designer (Standard). Platform Designer (Pro) introduces hierarchical isolation between system interconnect and IP components.
- Block-Based Design Flows—preserve and reuse design blocks at various stages of compilation.
Intel® Quartus® Prime Pro Edition software does not support the following Intel® Quartus® Prime Standard Edition features:
- I/O Timing Analysis
- NativeLink third party tool integration (other third-party tool integration available)
- Video and Image Processing Suite IP Cores
- Talkback features
- Various register merging and duplication settings
- Saving a node-level netlist as .vqm or RTL to schematic conversion
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