4.10. Plan for On-Chip Debugging Tools
The Intel® Quartus® Prime in-system debugging tools offer different advantages and trade-offs, depending on the characteristics of your design. Consider the following debugging requirements when planning your design to support debugging tools:
- JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.
- Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic.
- Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging.
- Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which require I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required. Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation.
- Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core.
- Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the tapped node names do not change during synthesis.
Table 15. Factors to Consider When Using Debugging Tools During Design Planning Stages Design Planning Factor Signal Tap
System Console In-System Memory
Logic Analyzer Interface (LAI) Signal Probe In-System Sources
Virtual JTAG IP Core JTAG connections Yes Yes Yes Yes — Yes Yes Additional logic resources — Yes — — — — Yes Reserve device memory Yes Yes — — — — — Reserve I/O pins — — — Yes Yes — — Instantiate IP core in your HDL code — — — — — Yes Yes