Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 6/20/2022
Public
Document Table of Contents

2.4. Introduction to Intel® Quartus® Prime Pro Edition Revision History

Document Version Intel® Quartus® Prime Version Changes
2022.06.20 22.2
  • Added new Top FAQs navigation to document cover.
  • Revised Introduction to add FPGA definition and device selection footnote.
  • Added new FPGA Basic Design Prerequisites topic.
  • Added new Experiment with a Design Example topic.
2020.09.28 20.3
  • Updated GUI screenshot in Introduction.
2019.09.30 19.3
  • Added compilation support for Intel® Agilex™ devices.
2018.09.24 18.1
  • Added screenshot of Intel® Quartus® Prime Pro Edition GUI.
2018.05.07 18.0 Initial release as separate chapter of Getting Started User Guide. Separated Migrating to Intel® Quartus® Prime Pro Edition as independent chapter in user guide.
2017.11.06 17.1
  • Described Intel® Quartus® Prime tool name updates for Platform Designer (Qsys), Interface Planner (BluePrint), Timing Analyzer (TimeQuest), Eye Viewer (EyeQ), and Advanced Link Analyzer (Advanced Link Analyzer).
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
2017.05.08 17.0
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
  • Added reference to Block-Based Design Flows.
  • Removed procedure on manual dynamic synthesis report generation. The Compiler automatically generates dynamic synthesis reports when enabled.
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Added reference to Partial Reconfiguration support.
  • Added to list of Intel® Quartus® Prime Standard Edition features unsupported by Intel® Quartus® Prime Pro Edition.
  • Added topic on Safe State Machine encoding.
  • Described unsupported Intel® Quartus® Prime Standard Edition physical synthesis options.
  • Removed deprecated Per-Stage Compilation (Beta) Compilation Flow.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
2016.05.03 16.0
  • Removed software beta status and revised feature set.
  • Added topic on Safe State Machine encoding.
  • Added Generating Dynamic Synthesis Reports.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Added description of Fitter Plan, Place and Route stages, reporting, and optimization.
  • Added Per-Stage Compilation (Beta) Compilation Flow.
  • Added Platform Designer information.
  • Added OpenCL and Signal Tap with routing preservation as unique Pro Edition features.
  • Clarified limitations for multiple Logic Lock instances in the same region.
2015.11.02 15.1
  • First version of document.

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