Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 6/20/2022
Public
Document Table of Contents

5.9.2.1. Generating a Combined Simulator Setup Script

You can run the Generate Simulator Setup Script for IP command to generate a combined simulator setup script.

You can then source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:

  • IP core initial generation or regeneration with new parameters
  • Intel® Quartus® Prime software version upgrade
  • IP core version upgrade
ip-setup-simulation Utility
Utility Syntax
ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible.
ip-setup-simulation
 --quartus-project=<my proj>
 --output-directory=<my_dir>
 --use-relative-paths
 --compile-to-work

--use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.

To generate a combined simulator setup script for all project IP cores for each simulator:3
  1. Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
    Note: For designs with F-tile IP, do not turn on the Use top-level entity names from Quartus project option.
    Figure 57. Generate Simulator Setup Script for IP Dialog Box


  2. To incorporate the generated simulator setup script into your top-level simulation script, refer to the template section in the generated simulator setup script as a guide to creating a top-level script:
    1. Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
    2. Remove the comments at the beginning of each line from the copied template sections.
    3. Specify the customizations you require to match your design simulation requirements, for example:
      • Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
      • If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
      • Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
  3. Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.

Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts

Follow these steps to incorporate the generated ActiveHDL* or Riviera Pro* simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.do.
    # # Start of template 
    # # If the copied and modified template file is "aldec.do", run it as: 
    # # vsim -c -do aldec.do 
    # # 
    # # Source the generated sim script 
    # source rivierapro_setup.tcl 
    # # Compile eda/sim_lib contents first 
    # dev_com 
    # # Override the top-level name (so that elab is useful) 
    # set TOP_LEVEL_NAME top 
    # # Compile the standalone IP. 
    # com 
    # # Compile the top-level 
    # vlog -sv2k5 ../../top.sv 
    # # Elaborate the design. 
    # elab 
    # # Run the simulation 
    # run 
    # # Report success to the shell 
    # exit -code 0 
    # # End of template
  2. Delete the first two characters of each line (comment and space):
    # Start of template 
    # If the copied and modified template file is "aldec.do", run it as: 
    # vsim -c -do aldec.do 
    # 
    # Source the generated sim script 
    source rivierapro_setup.tcl 
    # Compile eda/sim_lib contents first 
    dev_com 
    # Override the top-level name (so that elab is useful) 
    set TOP_LEVEL_NAME top 
    # Compile the standalone IP. 
    com 
    # Compile the top-level 
    vlog -sv2k5 ../../top.sv 
    # Elaborate the design. 
    elab 
    # Run the simulation 
    run 
    # Report success to the shell 
    exit -code 0
    # End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
    set TOP_LEVEL_NAME sim_top
     vlog –sv2k5 ../../sim_top.sv
  4. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  5. Run the new top-level script from the generated simulation directory:
    vsim –c –do <path to sim_top>.tcl

Sourcing Cadence Incisive* Simulator Setup Scripts

Follow these steps to incorporate the generated Cadence Incisive* IP simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, ncsim.sh.
    # # Start of template
    # # If the copied and modified template file is "ncsim.sh", run it as:
    # # ./ncsim.sh
    # # 
    # # Do the file copy, dev_com and com steps
    # source ncsim_setup.sh
    # SKIP_ELAB=1
    # SKIP_SIM=1
    # 
    # # Compile the top level module
    # ncvlog -sv "$QSYS_SIMDIR/../top.sv"
    # 
    # # Do the elaboration and sim steps
    # # Override the top-level name
    # # Override the sim options, so the simulation
    # # runs forever (until $finish()). 
    # source ncsim_setup.sh
    # SKIP_FILE_COPY=1
    # SKIP_DEV_COM=1
    # SKIP_COM=1
    # TOP_LEVEL_NAME=top
    # USER_DEFINED_SIM_OPTIONS=""
    # # End of template
  2. Delete the first two characters of each line (comment and space):
    # Start of template
    # If the copied and modified template file is "ncsim.sh", run it as:
    # ./ncsim.sh
    # 
    # Do the file copy, dev_com and com steps
    source ncsim_setup.sh
    SKIP_ELAB=1
    SKIP_SIM=1
    # Compile the top level module
    ncvlog -sv "$QSYS_SIMDIR/../top.sv"
    # Do the elaboration and sim steps
    # Override the top-level name
    # Override the sim options, so the simulation
    # runs forever (until $finish()).
    source ncsim_setup.sh
    SKIP_FILE_COPY=1
    SKIP_DEV_COM=1
    SKIP_COM=1
    TOP_LEVEL_NAME=top
    USER_DEFINED_SIM_OPTIONS=""
    # End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
    TOP_LEVEL_NAME=sim_top \
          ncvlog -sv "$QSYS_SIMDIR/../top.sv"
  4. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  5. Run the resulting top-level script from the generated simulation directory by specifying the path to ncsim.sh.

Sourcing Cadence Xcelium* Simulator Setup Scripts

  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, xmsim.sh.
    # #Start of template
    # # Xcelium Simulation Script.
    # # If the copied and modified template file is "xmsim.sh", run it as:
    # # ./xmsim.sh 
    # # 
    # # Do the file copy, dev_com and com steps 
    # source <script generation output directory>/xcelium/xcelium_setup.sh \
    # SKIP_ELAB=1 \
    # SKIP_SIM=1 \
    # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
    # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your 
    # design> \
    # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for  
    # your design> \
    # QSYS_SIMDIR=<script generation output directory>
    # #
    # # Compile all design files and testbench files, including the top level.
    # # (These are all the files required for simulation other than the files
    # # compiled by the IP script)
    # #
    # xmvlog <compilation options> <design and testbench files>
    # #
    # # TOP_LEVEL_NAME is used in this script to set the top-level simulation
    # # or testbench module/entity name.
    # #
    # # Run the IP script again to elaborate and simulate the top level:
    # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
    # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
    # #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
    # #
    # source <script generation output directory>/xcelium/xcelium_setup.sh \
    # SKIP_FILE_COPY=1 \
    # SKIP_DEV_COM=1 \
    # SKIP_COM=1 \
    # TOP_LEVEL_NAME=<simulation top> \
    # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
    # USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
    # # End of template
  2. Delete the first two characters of each line (comment and space):
    # Start of template
    # Xcelium Simulation Script (Beta Version).
    # If the copied and modified template file is "xmsim.sh", run it as:
    # ./xmsim.sh 
    # 
    # Do the file copy, dev_com and com steps 
    source <script generation output directory>/xcelium/xcelium_setup.sh \
    SKIP_ELAB=1 \
    SKIP_SIM=1 \
    USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
    USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
    USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
    QSYS_SIMDIR=<script generation output directory>
    #
    # Compile all design files and testbench files, including the top level.
    # (These are all the files required for simulation other than the files
    # compiled by the IP script)
    #
    xmvlog <compilation options> <design and testbench files>
    #
    # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
    # testbench module/entity name.
    #
    # Run the IP script again to elaborate and simulate the top level:
    # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
    # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
    #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
    #
    source <script generation output directory>/xcelium/xcelium_setup.sh \
    SKIP_FILE_COPY=1 \
    SKIP_DEV_COM=1 \
    SKIP_COM=1 \
    TOP_LEVEL_NAME=<simulation top> \
    USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
    USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
    # End of template
  3. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  4. Run the resulting top-level script from the generated simulation directory by specifying the path to xmsim.sh.

Sourcing ModelSim* or QuestaSim Simulator Setup Scripts

Follow these steps to incorporate the generated ModelSim* or QuestaSim IP simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.do.
    # # Start of template
    # # If the copied and modified template file is "mentor.do", run it
    # # as: vsim -c -do mentor.do
    # # 
    # # Source the generated sim script
    # source msim_setup.tcl
    # # Compile eda/sim_lib contents first
    # dev_com
    # # Override the top-level name (so that elab is useful)
    # set TOP_LEVEL_NAME top
    # # Compile the standalone IP.
    # com
    # # Compile the top-level
    # vlog -sv ../../top.sv
    # # Elaborate the design.
    # elab
    # # Run the simulation
    # run -a
    # # Report success to the shell
    # exit -code 0
    # # End of template
  2. Delete the first two characters of each line (comment and space):
    # Start of template
    # If the copied and modified template file is "mentor.do", run it
    # as: vsim -c -do mentor.do
    # 
    # Source the generated sim script source msim_setup.tcl
    # Compile eda/sim_lib contents first
    dev_com
    # Override the top-level name (so that elab is useful)
    set TOP_LEVEL_NAME top
    # Compile the standalone IP.
    com
    # Compile the top-level vlog -sv ../../top.sv
    # Elaborate the design.
    elab
    # Run the simulation
    run -a
    # Report success to the shell
    exit -code 0
    # End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the location of the simulation's top-level file. For example:
    set TOP_LEVEL_NAME sim_top vlog -sv ../../sim_top.sv
  4. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  5. Run the resulting top-level script from the generated simulation directory:
    vsim –c –do <path to sim_top>.tcl

Sourcing Synopsys VCS* Simulator Setup Scripts

Follow these steps to incorporate the generated Synopsys VCS* simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains these template lines. Cut and paste the lines preceding the “helper file” into a new executable file. For example, synopsys_vcs.f.
    # # Start of template
    # # If the copied and modified template file is "vcs_sim.sh", run it
    # # as: ./vcs_sim.sh
    # # 
    # # Override the top-level name
    # # specify a command file containing elaboration options
    # # (system verilog extension, and compile the top-level).
    # # Override the sim options, so the simulation
    # # runs forever (until $finish()).
    # source vcs_setup.sh
    # TOP_LEVEL_NAME=top
    # USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'"
    # USER_DEFINED_SIM_OPTIONS=""
    # 
    # # helper file: synopsys_vcs.f
    # +systemverilogext+.sv
    # ../../../top.sv
    # # End of template
  2. Delete the first two characters of each line (comment and space) for the vcs.sh file, as shown below:
    # Start of template
    # If the copied and modified template file is "vcs_sim.sh", run it
    # as: ./vcs_sim.sh
    # 
    # Override the top-level name
    # specify a command file containing elaboration options
    # (system verilog extension, and compile the top-level).
    # Override the sim options, so the simulation
    # runs forever (until $finish()).
    source vcs_setup.sh
    TOP_LEVEL_NAME=top
    USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'"
    USER_DEFINED_SIM_OPTIONS=""
  3. Delete the first two characters of each line (comment and space) for the synopsys_vcs.f file, as shown below:
    # helper file: synopsys_vcs.f
     +systemverilogext+.sv
     ../../../top.sv
    # End of template
  4. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
    TOP_LEVEL_NAME=sim_top
  5. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  6. Run the resulting top-level script from the generated simulation directory by specifying the path to vcs_sim.sh.

Sourcing Synopsys VCS MX Simulator Setup Scripts

Follow these steps to incorporate the generated Synopsys VCS* MX simulation scripts for use in top-level project simulation scripts.
  1. The generated simulation script contains these template lines. Cut and paste the lines preceding the “helper file” into a new executable file. For example, vcsmx.sh.
    # # Start of template
    # # If the copied and modified template file is "vcsmx_sim.sh", run
    # # it as: ./vcsmx_sim.sh
    # # 
    # # Do the file copy, dev_com and com steps
    # source vcsmx_setup.sh
    # SKIP_ELAB=1
          
    # SKIP_SIM=1
    # 
    # # Compile the top level module 
    # vlogan +v2k
         +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
      
    # # Do the elaboration and sim steps
    # # Override the top-level name
    # # Override the sim options, so the simulation runs
    # # forever (until $finish()).
    # source vcsmx_setup.sh
    # SKIP_FILE_COPY=1
    # SKIP_DEV_COM=1
    # SKIP_COM=1
    # TOP_LEVEL_NAME="'-top top'"
    # USER_DEFINED_SIM_OPTIONS=""
    # # End of template
  2. Delete the first two characters of each line (comment and space), as shown below:
    # Start of template
    # If the copied and modified template file is "vcsmx_sim.sh", run
    # it as: ./vcsmx_sim.sh
    # 
    # Do the file copy, dev_com and com steps
    source vcsmx_setup.sh
    SKIP_ELAB=1
    SKIP_SIM=1
      
    # Compile the top level module
    vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
       
    # Do the elaboration and sim steps
    # Override the top-level name
    # Override the sim options, so the simulation runs
    # forever (until $finish()).
    source vcsmx_setup.sh
    SKIP_FILE_COPY=1
    SKIP_DEV_COM=1
    SKIP_COM=1
    TOP_LEVEL_NAME="'-top top'"
    USER_DEFINED_SIM_OPTIONS=""
    # End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
    TOP_LEVEL_NAME=”'-top sim_top'” 
  4. Make the appropriate changes to the compilation of your top-level file, for example:
    vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"
  5. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  6. Run the resulting top-level script from the generated simulation directory by specifying the path to vcsmx_sim.sh.
3 If your design contains one or more F-tile IPs, you must first perform Start Analysis & Elaboration and then Support-Logic Generation before performing these steps.

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