Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Pending Deprecation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

Document Version Intel® HLS Compiler Pro Edition Version Changes
2022.12.19 22.4
  • Added pending deprecation notice.
  • Updated <quartus_installdir> path information for Version 22.4.
2022.09.23 22.3
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 22.3.

2022.06.20 22.2
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 22.2.

2022.03.28 22.1
  • Maintenance release.

    Updated <quartus_installdir> path information for Version 22.1.

2021.12.13 21.4
2021.10.04 21.3
  • Replaced references to Mentor® ModelSim® with Siemens® EDA Questa®.
2021.06.21 21.2
  • Revised references to Avalon Interfaces to align with new Avalon Interconnect terminology. Avalon master interfaces are now Avalon host interfaces, and Avalon slave interfaces are now Avalon agent interfaces.
2021.03.29 21.1
2020.12.14 20.4
2020.08.28 20.3
2020.06.22 20.2
2020.04.14 20.1
2019.12.16 19.4

Document Revision History for Intel® HLS Compiler User Guide

Previous versions of the Intel® HLS Compiler User Guide contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.

Document Version Intel® Quartus® Prime Version Changes
2019.09.30 19.3
2019.07.01 19.2
  • Updated Reviewing the High-Level Design Reports (report.html) to reflect the merging of various viewers into the Graph Viewer (beta). Some images in the section do not reflect the new reporting interface. The images will be updated in a future release of this document.
2019.04.01 19.1
2019.01.03 18.1.1
2018.12.24 18.1.1
2018.09.24 18.1
2018.07.02 18.0
2018.05.07 18.0
  • Starting with Intel® Quartus® Prime Version 18.0, the features and devices supported by the Intel® HLS Compiler depend on what edition of Intel® Quartus® Prime you have. Intel® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows:
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.
  • Added important prerequisite for Intel® MAX® 10 users to Synthesize your Component IP with Intel® Quartus® Prime Standard Edition .
  • Revised Debugging during Verification to clarify how to view the waveform in ModelSim* after simulation.
2017.12.22 17.1.1
  • Corrected typos in Execution Model:
    • ihs_hls_component_run_all is now ihc_hls_component_run_all.
    • ihs_hls_run_all_enqueued is now ihc_hls_component_run_all.
2017.11.06 17.1
2017.06.23 —
  • Minor changes and corrections.
2017.06.09 —
2017.02.03 —
  • Added note about what functions have components synthesized for them when you run the i++ command.
  • Under Reviewing Your Component's report.html File, added Component memory viewer section to introduce the Component memory viewer report.
  • Under Reviewing Your Component's report.html File, updated examples and screen captures to reflect examples and tutorials provided with the Intel® HLS Compiler.
  • Updated the values for the __ALTERA_COMPILER__ HLS compiler-defined preprocessor macro.
2016.11.30 —
  • Under Reviewing Your Component's report.html File, added the Information on Component Verification Results section to introduce the Verification Statistics report.
  • In Verifying Your HLS IP, noted that information on the supported versions of the ModelSim software is available in the Intel® Quartus® Prime Software and Device Support Release Notes.
  • Removed the Latency Measurement during Verification section because the APIs described within have been removed.
  • In Adding the Compiler-Generated IP into a Intel® Quartus® Prime Project and Adding the Compiler-Generated IP into a Qsys System, specified that the for the Intel® Quartus® Prime Standard Edition software, the file in question is the .qsys file. For the Intel® Quartus® Prime Pro Edition software, the file in question is the .ip file.
  • Updated the Limitations of the HLS Compiler section:
    • Removed the limitation on ModelSim software version support.
    • Added the limitation that C++ library calls are not supported on Windows.
2016.09.12 —
  • Initial release.
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