6. Verifying Your IP with Simulation
The Intel® HLS Compiler Pro Edition uses Siemens® EDA Questa® software to perform the simulation. You must have Questa® installed to use the Intel® HLS Compiler. For a list of supported versions of the Questa® software, refer to the EDA Interface Information section in the Intel® Quartus® Prime Software and Device Support Release Notes.
Verifying the functionality of your design in this way is sometimes called debugging through simulation.
- Run the executable that the compiler generates by targeting the FPGA architecture. By default, the name of the executable is a.out (Linux) or a.exe (Windows).
For example, you might invoke a command like tone of the following commands for a simple single-file design:
- Linux: i++ -march="Arria10" […] design.cpp && ./a.out
- Windows: i++ -march="Arria10" […] design.cpp && a.exe
- Write variable values to output streams at certain points in your code.
- Review the waveforms generated when running your design.
The compiler does not log signals by default when you compile your design. To enable signal logging in simulation, refer to Debugging during Verification.
Did you find the information on this page useful?