1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
6. Verifying Your IP with Simulation
When compiling your component to an FPGA architecture, the Intel® HLS Compiler Pro Edition links your design C++ testbench with an RTL-compiled version of your component that runs in an RTL simulator.
The Intel® HLS Compiler Pro Edition uses Siemens® EDA Questa® software to perform the simulation. You must have Questa® installed to use the Intel® HLS Compiler. For a list of supported versions of the Questa® software, refer to the EDA Interface Information section in the Intel® Quartus® Prime Software and Device Support Release Notes.
Verifying the functionality of your design in this way is sometimes called debugging through simulation.
To verify the functionality of your design from the simulation of your design you can use debugging techniques like the following:
- Run the executable that the compiler generates by targeting the FPGA architecture. By default, the name of the executable is a.out (Linux) or a.exe (Windows).
For example, you might invoke a command like tone of the following commands for a simple single-file design:
- Linux: i++ -march="Arria10" […] design.cpp && ./a.out
- Windows: i++ -march="Arria10" […] design.cpp && a.exe
- Write variable values to output streams at certain points in your code.
- Review the waveforms generated when running your design.
The compiler does not log signals by default when you compile your design. To enable signal logging in simulation, refer to Debugging during Verification.
Generation of the Verification Testbench Executable
Debugging during Verification
High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
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