6.2. Debugging during Verification
By default, the HLS compiler instructs the simulator not to log any signals because logging signals slows the simulation, and the waveforms files can be very large. However, you can configure the compiler to save these waveforms for debugging purposes.
Specify the <depth> attribute to specify how many levels of hierarchy are logged. Specify -ghdl=1 to log only top level signals. If you do not specify the <depth> attribute, all signals are logged.
i++ -march="<FPGA_family_or_part_number>" -ghdl[=<depth>] <input files>
When the simulation finishes, open the vsim.wlf file inside the <result>.prj/verification directory to view the waveform.
To view the waveform after the simulation finishes:
- In Questa®, open the vsim.wlf file inside the <result>.prj/verification directory.
- Right-click the <component_name>_inst block and select Add Wave.
You can now view the component top-level signals: start, busy, stall, done, parameters, and outputs. Use the waveform to see how the component interacts with its interfaces.Tip:
When you view the simulation waveform in Questa®, the simulation clock period is set to a default value of 1000 picoseconds (ps). To synchronize the Time axis to show one cycle per tick mark, change the time resolution from picoseconds (ps) to nanoseconds (ns):
- Right-click the timeline and select Grid, Timeline & Cursor Control.
- Under Timeline Configuration, set the Time units to ns.
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