Visible to Intel only — GUID: dkf1522253536321
Ixiasoft
Visible to Intel only — GUID: dkf1522253536321
Ixiasoft
A.5. Accessing HLD FPGA Reports in JSON Format
The JSON files containing the data are available in the <result>.prj/reports/lib/json directory. The directory provides the following .json files:
File | Description |
---|---|
area.json | Area Analysis of System |
area_src.json | Area Analysis of Source (deprecated) |
block.json | Block View of System Viewer |
bottleneck.json | Bottleneck View of Loop Analysis Report and Schedule Viewer |
info.json | Summary of project name, compilation command, versions, and timestamps |
loops.json | Navigation tree of Loop Analysis report |
loops_attr.json | Loop Analysis report |
mav.json | Function View of System Viewer |
new_lmv.json | Function Memory Viewer |
pipeline.json | Cluster View of System Viewer |
quartus.json | Quartus Prime compilation summary |
summary.json | Component compilation name mapping |
system.json | System View of System Viewer |
tree.json | Navigation tree of System Viewer |
warnings.json | Compilation warning messages |
You can read the following .json files without a special parser:
- area.json
- area_src.json
- loops.json
- quartus.json
- summary.json
For example, if you want to identify all of the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the children section in the loops.json file, as shown below:
“name”:”<block name|Component: component name> # Find the loops which does not begin with “Component:” “data”:[<Yes|No>, <#|n/a>, <II|n/a>] # The data field corresponds to “Pipelined”, “II”, “Bottleneck”
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