F-Tile Ethernet Intel® FPGA Hard IP Release Notes

ID 683443
Date 4/01/2024

1.7. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0

Table 7.  v7.0.0 2022.09.26
Quartus® Prime Version Description Impact
22.3 Added new parameter: 32-bit Soft CWBIN Counters

Available when FEC mode is selected. When enabled, converts 8-bit CWBin0-3 registers in Ethernet Hard IP to 32-bit registers in soft logic.

Updated timestamp accuracy in basic and advanced modes. The timestamp accuracy values in the Basic and Advanced modes reflect simulation and hardware results.
Added new parameter: Enable dedicated CDR Clock Output
Priority-based Flow Control (PFC) support is disabled for 200G/400G variants.

IP migration to full rate Phase-Locked Loop (PLL) for both FHT and FGT transceivers.

Force upgrade to current release.