F-Tile Ethernet Intel® FPGA Hard IP Release Notes

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ID 683443
Date 5/02/2025
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1. F-Tile Ethernet Intel FPGA Hard IP Release Notes
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes x
1.1. F-Tile Ethernet Intel® FPGA Hard IP v18.0.0 1.2. F-Tile Ethernet Intel® FPGA Hard IP v17.0.0 1.3. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0 1.4. F-Tile Ethernet Intel® FPGA Hard IP v15.0.0 1.5. F-Tile Ethernet Intel® FPGA Hard IP v14.0.0 1.6. F-Tile Ethernet Intel® FPGA Hard IP v12.0.0 1.7. F-Tile Ethernet Intel® FPGA Hard IP v11.0.0 1.8. F-Tile Ethernet Intel® FPGA Hard IP v10.0.0 1.9. F-Tile Ethernet Intel® FPGA Hard IP v9.0.0 1.10. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0 1.11. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0 1.12. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0 1.13. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0 1.14. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0 1.15. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0 1.16. F-Tile Ethernet Intel® FPGA Hard IP v2.0.0 1.17. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 1.18. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes

1.11. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0

Table 11.  v7.0.0 2022.09.26
Quartus® Prime Version Description Impact
22.3 Added new parameter: 32-bit Soft CWBIN Counters.

Available when FEC mode is selected. When enabled, converts 8-bit CWBin0-3 registers in Ethernet Hard IP to 32-bit registers in soft logic.

Updated timestamp accuracy in basic and advanced modes. The timestamp accuracy values in the Basic and Advanced modes reflect simulation and hardware results.
Added new parameter: Enable dedicated CDR Clock Output. —
Priority-based Flow Control (PFC) support is disabled for 200G/400G variants. —

IP migration to full rate Phase-Locked Loop (PLL) for both FHT and FGT transceivers.

 Force upgrade to current release.
Level Two Title