1.5. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0
|Intel® Quartus® Prime Version||Description||Impact|
|21.3||Added support for the fast simulation model for FGT variants.||Enabled by default for generated design examples. To enable the feature in your own design simulation, add the fast sim macro in your simulation script.|
|Updated timestamp accuracy in basic and advanced modes.||The timestamp accuracy values in the Basic and Advanced modes reflect simulation results only. Hardware accuracy values may differ and will be available in a future release.|
|Added new parameter: Enable Ethernet debug endpoint||When enabled, allows you to access the Ethernet toolkit via System Console.|
|Added VHDL file format support.||—|
|Added support for Siemens EDA* Questa* and Questa-Intel FPGA Edition simulator.||—|
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