F-Tile Ethernet Intel® FPGA Hard IP Release Notes

ID 683443
Date 7/08/2024
Public

1.7. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0

Table 7.  v8.0.0 2022.12.19
Quartus® Prime Version Description Impact
22.4 Updated support for the HDL file format in the following simulators:
  • Synopsys VCS* (Verilog)
  • Synopsys VCS* MX (VHDL/Verilog)
  • Cadence* Xcelium* (VHDL/Verilog)
  • Siemens EDA* ModelSim* SE (VHDL/Verilog)
  • QuestaSim* (VHDL/Verilog)
  • Aldec Riviera-PRO (VHDL/Verilog)
Added new parameter: Advanced mode When turned on, enables the Custom Ethernet line rate.
Added new parameter: Include Deterministic Latency Measurement When turned on, enables the built-in Deterministic Latency Measurement module within the IP.