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1.1. F-Tile Ethernet Intel® FPGA Hard IP v18.0.0
1.2. F-Tile Ethernet Intel® FPGA Hard IP v17.0.0
1.3. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0
1.4. F-Tile Ethernet Intel® FPGA Hard IP v15.0.0
1.5. F-Tile Ethernet Intel® FPGA Hard IP v14.0.0
1.6. F-Tile Ethernet Intel® FPGA Hard IP v12.0.0
1.7. F-Tile Ethernet Intel® FPGA Hard IP v11.0.0
1.8. F-Tile Ethernet Intel® FPGA Hard IP v10.0.0
1.9. F-Tile Ethernet Intel® FPGA Hard IP v9.0.0
1.10. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0
1.11. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0
1.12. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0
1.13. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0
1.14. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0
1.15. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0
1.16. F-Tile Ethernet Intel® FPGA Hard IP v2.0.0
1.17. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
1.18. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
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1.14. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0
Quartus® Prime Version | Description | Impact |
---|---|---|
21.4 | Added new parameter: Enable FHT pre-encoder. | When enabled, allows the FHT precoding for PAM4 designs. |
Added new parameter: Enable Native PHY Debug Endpoint. | When enabled, allows you to access the Ethernet toolkit via internal JTAG interface. The Quartus® Prime software version 21.4 supports transceiver toolkit for a single transceiver channel. | |
Updated Quartus® Prime software Support-Logic Generation step. | The Support-Logic Generation command runs automatically when you generate your design using F-Tile Ethernet Intel® FPGA Hard IP Example Design IP Parameter Editor. | |
Added support for Cadence* Xcelium* simulator. | — |