F-Tile Ethernet Intel® FPGA Hard IP Release Notes

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ID 683443
Date 5/02/2025
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1. F-Tile Ethernet Intel FPGA Hard IP Release Notes
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes x
1.1. F-Tile Ethernet Intel® FPGA Hard IP v18.0.0 1.2. F-Tile Ethernet Intel® FPGA Hard IP v17.0.0 1.3. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0 1.4. F-Tile Ethernet Intel® FPGA Hard IP v15.0.0 1.5. F-Tile Ethernet Intel® FPGA Hard IP v14.0.0 1.6. F-Tile Ethernet Intel® FPGA Hard IP v12.0.0 1.7. F-Tile Ethernet Intel® FPGA Hard IP v11.0.0 1.8. F-Tile Ethernet Intel® FPGA Hard IP v10.0.0 1.9. F-Tile Ethernet Intel® FPGA Hard IP v9.0.0 1.10. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0 1.11. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0 1.12. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0 1.13. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0 1.14. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0 1.15. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0 1.16. F-Tile Ethernet Intel® FPGA Hard IP v2.0.0 1.17. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 1.18. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes

1.13. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0

Table 13.  v5.0.0 2022.03.28
Quartus® Prime Version Description Impact
22.1 Added support for the Agilex I-Series Transceiver-SoC Development Kit. —
Added a new support_logic directory structure. When generating a design example, the hardware_test_design includes the new directory.
Added a new synthesis-related parameter: IP-XACT When enabled, generates the .ipxact files.
Added support for the VHDL file format in the following simulators:
  • Synopsys VCS* MX
  • Cadence* Xcelium*
  • Siemens EDA* ModelSim* SE
 —
Renamed parameter from Enable Native PHY Debug Endpoint to Enable debug endpoint for transceiver toolkit. —
Added multi lane support for transceiver toolkit. —
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