F-Tile Ethernet Intel® FPGA Hard IP Release Notes

ID 683443
Date 4/01/2024

1.9. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0

Table 9.  v5.0.0 2022.03.28
Quartus® Prime Version Description Impact
22.1 Added support for the Agilex I-Series Transceiver-SoC Development Kit.
Added a new support_logic directory structure. When generating a design example, the hardware_test_design includes the new directory.
Added a new synthesis-related parameter: IP-XACT When enabled, generates the .ipxact files.
Added support for the VHDL file format in the following simulators:
  • Synopsys VCS* MX
  • Cadence* Xcelium*
  • Siemens EDA* ModelSim* SE
Renamed parameter from Enable Native PHY Debug Endpoint to Enable debug endpoint for transceiver toolkit.
Added multi lane support for transceiver toolkit.