AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683428
Date 7/15/2019
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Document Table of Contents
Document Table of Contents x
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Static Update Partial Reconfiguration Tutorial Revision History
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Add the Partial Reconfiguration Controller IP 1.5.5. Step 5: Define Personas 1.5.6. Step 6: Create Revisions 1.5.7. Step 7: Compile the Base Revision 1.5.8. Step 8: Set Up PR Implementation Revisions 1.5.9. Step 9: Change the SUPR Logic 1.5.10. Step 10: Program the Board 1.5.11. Modifying the SUPR Partition
1.5.4. Step 4: Add the Partial Reconfiguration Controller IP x
1.5.4.1. Update the Top-Level Design
1.5.6. Step 6: Create Revisions x
1.5.6.1. Setting the Base Revision 1.5.6.2. Creating Implementation Revisions
1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board

1.5.4. Step 4: Add the Partial Reconfiguration Controller IP

The Partial Reconfiguration Controller IP enables reconfiguration over JTAG. The following steps describe adding the Partial Reconfiguration Controller IP core to your project.
Note: To skip these steps, copy the pr_ip.ip file from the pr folder into your project directory, and add the set_global_assignment -name IP_FILE pr_ip.ip assignment to the blinking_led.qsf file. To ensure appropriate constraining of the IP, place this assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc).
  1. In the IP Catalog (Tools > IP Catalog), type Partial Reconfiguration in the search field.
  2. Double-click Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  3. In the Create IP Variant dialog box, type pr_ip as the file name, and then click Create.
  4. Turn on Use as partial reconfiguration internal host, Enable JTAG debug mode, and Enable freeze interface. Turn off Enable Avalon-MM slave interface.
    Figure 6. Partial Reconfiguration Controller IP Core Parameters
  5. Click Generate HDL.
  6. In the Generation dialog box, accept the default settings and click Generate. The parameter editor generates the pr_ip.ip variation file and adds the file to the blinking_led project.

Section Content
Update the Top-Level Design

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