AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683428
Date 7/15/2019
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1.5.6. Step 6: Create Revisions

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.

From the base revision, you create additional revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

To compile a PR design, you create a PR implementation revision for each persona. In addition, you must assign either the Partial Reconfiguration - Base or Partial Reconfiguration - Persona Implementation revision type for each of the revisions. The following table lists the revision name and the revision type for each of the revisions. The impl_blinking_led_supr_new.qsf revision is the SUPR persona implementation.

Table 3.  Revision Names and Types
Revision Name Revision Type
blinking_led.qsf Partial Reconfiguration - Base
blinking_led_default.qsf Partial Reconfiguration - Persona Implementation
blinking_led_slow.qsf Partial Reconfiguration - Persona Implementation
blinking_led_empty.qsf Partial Reconfiguration - Persona Implementation
impl_blinking_led_supr_new.qsf Partial Reconfiguration - Persona Implementation

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