AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683428
Date 7/15/2019
Public

1. Static Update Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 19.1
This application note demonstrates static update partial reconfiguration (SUPR) on the Intel® Arria® 10 GX FPGA development board.

Partial reconfiguration (PR) allows you to reconfigure a portion of an Intel® FPGA dynamically, while the remaining FPGA continues to operate. PR implements multiple personas in a particular region in your design, without impacting operation in areas outside this region. This methodology provides the following advantages in systems in which multiple functions time-share the same FPGA resources:

  • Allows run-time reconfiguration
  • Increases design scalability
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption by efficient use of board space

In traditional PR, any change to the static region requires recompilation of every persona. However, you can define a specialized SUPR region that allows change, without requiring the recompilation of personas. This technique is useful for a portion of a design that you may possibly want to change for risk mitigation, but that never requires runtime reconfiguration.

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