AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683428
Date 7/15/2019
Public
Download

1.5.4.1. Update the Top-Level Design

Update the top.sv file with the PR_IP instance:
  1. To add the pr_ip instance to the top-level design, uncomment the following code block in the top.sv file:
    pr_ip u_pr_ip
        (
            .clk           (clock),
            .nreset        (1'b1),
            .freeze        (freeze),
            .pr_start      (1'b0),            // ignored for JTAG
            .status        (pr_ip_status),
            .data          (16'b0),
            .data_valid    (1'b0),
            .data_ready    ()
        );
  2. To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. Uncomment the following lines of code:
    assign led_two_on_w    = freeze ? 1'b1 : pr_led_two_on;
    assign led_three_on_w  = freeze ? 1'b1 : pr_led_three_on;
    
  3. To assign an instance of the default persona (blinking_led), update the top.sv file with the following block of code:
    blinking_led u_blinking_led
        (
            .led_two_on    (pr_led_two_on),
            .led_three_on  (pr_led_three_on),
            .clock         (clock)
            .counter       (count_d)
        );
    Figure 7. Partial Reconfiguration IP Core Integration

Did you find the information on this page useful?

Characters remaining:

Feedback Message