AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683428
Date 7/15/2019

1.6. Static Update Partial Reconfiguration Tutorial Revision History

Document Version Intel® Quartus® Prime Version Changes
2019.07.15 19.1.0
  • Changed default file export location from output_files to project directory.
  • Described new reserved core partition type and related GUI.
  • Updated Design Partition Window descriptions and screenshots for column display button and new partition properties.
2018.10.12 18.1.0
  • Updated Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP name to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Added information about automated .qdb partition export to "Compile the Base Revision."
  • Added output_files directory to output paths.
  • Removed note about new simplified flow.
2018.06.18 18.0.0
  • Corrected syntax error in Define Personas topic code example.
  • Corrected syntax error in Change the SUPR Logic code example.
  • Updated screenshot in Change the SUPR Logic.
2018.05.07 18.0.0
  • Removed descriptions of obsolete synthesis-only revisions and corresponding personas. Replaced with latest simplified flow instructions.
  • Renamed PR revision names to match simplified PR flow.
  • Updated official name of Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP.
  • Added .qsf setting to automatically generate PR bitstream files after compilation.


Initial release of the document.