AN 817: Static Update Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683428
Date 7/15/2019
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1.5.5. Step 5: Define Personas

This reference design defines three separate personas for the single PR partition, and one SUPR persona for the SUPR region. Follow these steps to define and include these personas in your project. If using the Intel® Quartus® Prime Text Editor, disable Add file to current project when saving the files.
  1. Create new blinking_led_slow.sv, blinking_led_empty.sv, and top_counter_fast.sv SystemVerilog files in your working directory. Confirm that blinking_led.sv is already present in the working directory.
  2. Enter the following contents for the SystemVerilog files:
    Table 2.  Reference Design Personas SystemVerilog
    File Name Description Code
    blinking_led_slow.sv LEDs blink slower
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_slow (
         // clock
         input wire clock,
         input wire [31:0] counter,
         // Control signals for the LEDs
         output wire led_two_on,
         output wire led_three_on
    );
    
         localparam COUNTER_TAP = 27;
    
         reg led_two_on_r;
         reg led_three_on_r;
     
         assign led_two_on = led_two_on_r;
         assign led_three_on = led_three_on_r;
    
         always_ff @(posedge clock) begin
              led_two_on_r <= counter[COUNTER_TAP];
              led_three_on_r <= counter[COUNTER_TAP];
         end
    
    endmodule
    blinking_led_empty.sv LEDs stay ON
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_empty(
         // clock
         input wire clock,
         input wire [31:0] counter,
         // Control signals for the LEDs
         output wire led_two_on,
         output wire led_three_on
    );
    
         // LED is active low 
         assign led_two_on = 1'b0;
         
         assign led_three_on = 1'b0;
    
    endmodule
    top_counter_fast.sv Second SUPR persona
    `timescale 1 ps / 1 ps
    `default_nettype none 
    
    module top_counter_fast (
         // Control signals for the LEDs
         output wire led_one_on,
         output wire [31:0] count,
         // clock
         input wire clock
    );
    
         localparam COUNTER_TAP = 23;
         reg [31:0] count_d;
    
         assign count = count_d;
         assign led_one_on = count_d[COUNTER_TAP];
    
         always_ff @(posedge clock) begin
             count_d <= count_d + 2;
         end
    endmodule

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