NCO IP Core: User Guide

ID 683406
Date 11/06/2017
Document Table of Contents

1.2. NCO IP Core Features

  • 32-bit precision for angle and magnitude
  • Source interface compatible with the Avalon Interface Specification
  • Multiple NCO architectures:
    • Multiplier-based implementation using DSP blocks or logic elements (LEs), (single cycle and multi-cycle)
    • Parallel or serial CORDIC-based implementation
    • ROM-based implementation using embedded array blocks (EABs), embedded system blocks (ESBs), or external ROM
  • Single or dual outputs (sine/cosine)
  • Variable width frequency modulation input
  • Variable width phase modulation input
  • User-defined frequency resolution, angular precision, and magnitude precision
  • Frequency hopping
  • Multichannel capability
  • Simulation files and architecture-specific testbenches for VHDL and Verilog HDL
  • Dual-output oscillator and quaternary frequency shift keying (QFSK) modulator example designs