NCO IP Core: User Guide

ID 683406
Date 11/06/2017
Document Table of Contents

3.1.4. Multiplier-Based Architecture

The multiplier-based architecture uses multipliers to reduce memory usage. You can choose to implement the multipliers in either:
  • Logic elements (Cyclone series) or combinational ALUTs (Stratix series).
  • Dedicated multiplier circuitry (for example, dedicated DSP blocks) (Stratix or Arria series).
Note: When you specify a dual output multiplier-based NCO, the IP core provides an option to output a sample every two clock cycles. This setting reduces the throughput by a factor of two and halves the resources required by the waveform generation unit.
Table 7.  Architecture Comparison
Architecture Advantages
Large ROM Good for high speed and when a large quantity of internal memory is available. Gives the highest spectral purity and uses the fewest logic elements for a given parameterization.
Small ROM Good for high output frequencies with reduced internal memory usage when a lower SFDR is acceptable.
CORDIC High performance solution when internal memory is at a premium. The serial CORDIC architecture uses fewer resources than parallel although the throughput is reduced.
Multiplier-Based Reduced memory usage by implementing multipliers in logic elements or dedicated circuitry.