AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

ID 683327
Date 1/05/2021

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs connected to the FPGA. Selecting the output from particular counter bits causes the LEDs to blink at a specific frequency.

Figure 1. Flat Reference Design without PR Partitioning