AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

ID 683327
Date 1/05/2021

Programming the Child PR Region

The current version of the Intel® Quartus® Prime Pro Edition software does not provide a mechanism to check for incompatible child PR bitstreams for Intel® Stratix® 10 devices. So, it is very important that you program the correct child persona to match the parent persona.
Programming an incompatible bitstream on Intel® Stratix® 10 FPGA can result in one of the following:
  • Successful PR programming, but corrupted FPGA functionality
  • Unsuccessful PR programming, and corrupted FPGA functionality
If you wish to reprogram a child PR region on the FPGA, you must ensure that the child PR .rbf is generated from an implementation revision compile whose parent PR persona matches the persona currently on the FPGA. For example, when you program the base blinking_led.sof onto the FPGA, the parent PR persona is default. The child PR persona is default as well. To change the child PR persona to slow persona, you have the choice of using the following bitstreams:
  1. hpr_child_slow.pr_parent_partition.pr_partition.rbf
  2. hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf
In this case, you must choose the hpr_child_slow.pr_parent_partition.pr_partition.rbf bitstream, because the hpr_child_slow.pr_parent_partition.pr_partition.rbf is generated by an implementation revision that has the default parent persona. Choosing hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf results in unsuccessful PR programming, corrupted FPGA functionality, or both.