Reference Design Files
The partial reconfiguration tutorial reference design is available in the following location:
- Click Clone or download.
- Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/s10_pcie_devkit_blinking_led_hpr sub-folder to access the reference design.
Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.
|top_counter.sv||Top-level 32-bit counter that controls LED directly. The registered output of the counter controls LED, and powers LED and LED via the blinking_led module.|
Defines the timing constraints for the project.
|blinking_led.sv||In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED and LED.|
Intel® Quartus® Prime project file containing the list of all the revisions in the project.
Intel® Quartus® Prime settings file containing the assignments and settings for the project.
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