Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683315
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware x
1.6.1. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Simulation 2.4. Design Example Behavior 2.5. Design Example Registers 2.6. Design Example Interface Signals
2.5. Design Example Registers x
2.5.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide

2.4. Design Example Behavior

The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core. In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.

To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.

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