HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 1/26/2024
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.6. Design RTL Parameters

Use the HDMI TX and RX Top RTL parameters to customize the design example.

Most of the design parameters are available in the Design Example tab of the HDMI Intel® FPGA IP parameter editor. You can still change the design example settings you made in the parameter editor through the RTL parameters.

Table 21.  HDMI RX Top Parameters
Parameter Value Description
SUPPORT_DEEP_COLOR
  • 0: No deep color
  • 1: Deep color
 Determines if the core can encode deep color formats.
SUPPORT_AUXILIARY
  • 0: No AUX
  • 1: AUX
 Determines if the auxiliary channel encoding is included.
SYMBOLS_PER_CLOCK 8 Supports 8 symbols per clock for Intel® Cyclone® 10 GX devices.
SUPPORT_AUDIO
  • 0: No audio
  • 1: Audio
 Determines if the core can encode audio.
EDID_RAM_ADDR_WIDTH 8 (Default value) Log base 2 of the EDID RAM size.
BITEC_DAUGHTER_CARD_REV
  • 0: Not targeting any Bitec HDMI daughter card
  • 4: Supports Bitec HDMI daughter card revision 4
  • 6: Targeting Bitec HDMI daughter card revision 6
  • 11: Targeting Bitec HDMI daughter card revision 11 (default)
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.
POLARITY_INVERSION
  • 0: Do not invert polarity
  • 1: Invert polarity
 Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the rx_polinv port of the RX transceiver.
Table 22.  HDMI TX Top Parameters
Parameter Value Description
USE_FPLL 1 Supports fPLL as TX PLL only for Intel® Cyclone® 10 GX devices. Always set this parameter to 1.
SUPPORT_DEEP_COLOR
  • 0: No deep color
  • 1: Deep color
 Determines if the core can encode deep color formats.
SUPPORT_AUXILIARY
  • 0: No AUX
  • 1: AUX
 Determines if the auxiliary channel encoding is included.
SYMBOLS_PER_CLOCK 8 Supports 8 symbols per clock for Intel® Cyclone® 10 GX devices.
SUPPORT_AUDIO
  • 0: No audio
  • 1: Audio
 Determines if the core can encode audio.
BITEC_DAUGHTER_CARD_REV
  • 0: Not targeting any Bitec HDMI daughter card
  • 4: Supports Bitec HDMI daughter card revision 4
  • 6: Targeting Bitec HDMI daughter card revision 6
  • 11: Targeting Bitec HDMI daughter card revision 11 (default)
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.
POLARITY_INVERSION
  • 0: Do not invert polarity
  • 1: Invert polarity
 Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the tx_polinv port of the TX transceiver.
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