HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime Pro Edition software and open <project directory>/quartus/c10_hdmi2_demo.qpf.
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file will be generated in the <project directory>/quartus/output_files folder.
  5. In the Clock Controller, set the OUT7 frequency of Si5332 to 100 MHz.
  6. Connect to the on-board FMC (J7) Bitec HDMI 2.0 FMC Daughter Card.
  7. Connect TX (P1) of the Bitec HDMI 2.0 FMC Daughter Card to an external video source.
  8. Connect RX (P2) of the Bitec HDMI 2.0 FMC Daughter Card to an external video sink or video analyzer.
  9. Ensure all switches on the development board are in default position.
  10. Configure the selected Intel® Cyclone® 10 GX device on the development board using the generated .sof file (Tools > Programmer ).
  11. The analyzer should display the video generated from the source.
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