HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

ID 683309
Date 1/26/2024

A newer version of this document is available. Customers should click here to go to the newest version.

1.6. Design Limitation

You need to consider some limitations when instantiating the HDMI Intel® FPGA IP design examples.

  • You may encounter longer lock time using the HDMI RX for HDMI 2.0 resolution. This limitation will be resolved in a future release.
  • The HDMI RX core does not perform word alignment for HDMI 2.0 resolutions (data rate > 3.4 Gbps). The designs use the transceiver PCS word aligner (rtl/hdmi_rx/symbol_aligner.v) and control logic (rtl/reconfig_mgmt/*) to achieve fast word alignment.