1.6. Design Limitation
You need to consider some limitations when instantiating the HDMI Intel® FPGA IP design examples.
- You may encounter longer lock time using the HDMI RX for HDMI 2.0 resolution. This limitation will be resolved in a future release.
- The HDMI RX core does not perform word alignment for HDMI 2.0 resolutions (data rate > 3.4 Gbps). The designs use the transceiver PCS word aligner (rtl/hdmi_rx/symbol_aligner.v) and control logic (rtl/reconfig_mgmt/*) to achieve fast word alignment.
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