HDMI Intel® Cyclone 10 GX FGPA IP Design Example User Guide

Download
ID 683309
Date 9/07/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design example.

Hardware

  • Intel® Cyclone® 10 GX FPGA Development Kit
  • HDMI Source (Graphics Processor Unit (GPU))
  • HDMI Sink (Monitor)
  • Bitec HDMI FMC 2.0 daughter card (Revision 11)
  • HDMI cables
Note: You can select the revision of your Bitec HDMI daughter card. Set the local parameter BITEC_DAUGHTER_CARD_REV to 4, 6, or 11 in the top-level file (c10_hdmi2_demo.v ). When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.

Software

  • Intel® Quartus® Prime Pro Edition version 20.3 and later (for hardware testing)
  • ModelSim* - Intel® FPGA Edition, ModelSim* - Intel® FPGA Starter Edition, , Riviera-PRO* , VCS* (Verilog HDL only)/ VCS* MX, or Xcelium* Parallel simulator
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message