AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

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ID 683294
Date 6/13/2016
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 GX FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and AD9625 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 712 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

1.6. Test Results

The following table contains the possible results and their definition.

Table 8.  Results Definition

Result

Definition

PASS

The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with comments

The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL

The DUT was observed to exhibit non-conformant behavior.

Warning

The DUT was observed to exhibit behavior that is not recommended.

Refer to comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

Stratix V FPGA

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock and link clock frequencies.

Table 9.  Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Stratix V FPGA)

Set number

L

M

F

Subclass

SCR

K

Data rate (Mbps)

ADC Sampling Clock (MHz)

FPGA Link Clock (MHz)

Result

1

1

1

8

0

0

16

6250

156.25

156.25

Pass

2

1

1

8

0

1

16

6250

156.25

156.25

Pass

3

1

1

8

0

0

32

6250

156.25

156.25

Pass

4

1

1

8

0

1

32

6250

156.25

156.25

Pass

5

1

1

8

1

0

16

6250

156.25

156.25

Pass

6

1

1

8

1

1

16

6250

156.25

156.25

Pass

7

1

1

8

1

0

32

6250

156.25

156.25

Pass

8

1

1

8

1

1

32

6250

156.25

156.25

Pass

9

2

1

4

0

0

16

6250

625

156.25

Pass

10

2

1

4

0

1

16

6250

625

156.25

Pass

11

2

1

4

0

0

32

6250

625

156.25

Pass

12

2

1

4

0

1

32

6250

625

156.25

Pass

13

2

1

4

1

0

16

6250

625

156.25

Pass

14

2

1

4

1

1

16

6250

625

156.25

Pass

15

2

1

4

1

0

32

6250

625

156.25

Pass

16

2

1

4

1

1

32

6250

625

156.25

Pass

17

4

1

2

0

0

16

6250

1250

156.25

Pass

18

4

1

2

0

1

16

6250

1250

156.25

Pass

19

4

1

2

0

0

32

6250

1250

156.25

Pass

20

4

1

2

0

1

32

6250

1250

156.25

Pass

21

4

1

2

1

0

16

6250

1250

156.25

Pass

22

4

1

2

1

1

16

6250

1250

156.25

Pass

23

4

1

2

1

0

32

6250

1250

156.25

Pass

24

4

1

2

1

1

32

6250

1250

156.25

Pass

25

6

1

1

0

0

20

6250

2500

156.25

Pass with comments

26

6

1

1

0

1

20

6250

2500

156.25

Pass with comments

27

6

1

1

0

0

32

6250

2500

156.25

Pass with comments

28

6

1

1

0

1

32

6250

2500

156.25

Pass with comments

29

6

1

1

1

0

20

6250

2500

156.25

Pass with comments

30

6

1

1

1

1

20

6250

2500

156.25

Pass with comments

31

6

1

1

1

0

32

6250

2500

156.25

Pass with comments

32

6

1

1

1

1

32

6250

2500

156.25

Pass with comments

33

8

1

1

0

0

20

6250

2500

156.25

Pass

34

8

1

1

0

1

20

6250

2500

156.25

Pass

35

8

1

1

0

0

32

6250

2500

156.25

Pass

36

8

1

1

0

1

32

6250

2500

156.25

Pass

37

8

1

1

1

0

20

6250

2500

156.25

Pass

38

8

1

1

1

1

20

6250

2500

156.25

Pass

39

8

1

1

1

0

32

6250

2500

156.25

Pass

40

8

1

1

1

1

32

6250

2500

156.25

Pass

Table 10.  Results For Deterministic Latency Test (Stratix V FPGA)

Test

L

M

F

Subclass

K

Data rate (Mbps)

ADC Sampling Clock (MHz)

FPGA Link Clock (MHz)

Result

DL.1

1

1

8

1

32

6250

312.5

156.25

Pass

DL.2

1

1

8

1

32

6250

312.5

156.25

Pass

DL.3

1

1

8

1

32

6250

312.5

156.25

Pass with comments.

Link clock observed = 323

DL.1

2

1

4

1

32

6250

625

156.25

Pass

DL.2

2

1

4

1

32

6250

625

156.25

Pass

DL.3

2

1

4

1

32

6250

625

156.25

Pass with comments.

Link clock observed = 163 with FPGA LMFC offset = 0x1C at IP core register 0x54.

DL.1

4

1

2

1

32

6250

1250

156.25

Pass

DL.2

4

1

2

1

32

6250

1250

156.25

Pass

DL.3

4

1

2

1

32

6250

1250

156.25

Pass with comments.

Link clock observed = 99-100 with ADC LMFC offset register set to 0x14.

DL.1

6

1

1

1

32

6250

2500

156.25

Pass

DL.2

6

1

1

1

32

6250

2500

156.25

Pass

DL.3

6

1

1

1

32

6250

2500

156.25

Pass with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x02.

DL.1

8

1

1

1

32

6250

2500

156.25

Pass

DL.2

8

1

1

1

32

6250

2500

156.25

Pass

DL.3

8

1

1

1

32

6250

2500

156.25

Pass with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0x02.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 9.  Deterministic Latency Measurement Ramp Test Pattern Diagram (Stratix V FPGA)


Arria 10 GX FPGA

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock,link clock, and SYSREF frequencies.

Table 11.  Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 (Arria 10 GX FPGA)
Test L M F Subclass SCR K Data Rate (Gbps) Sampling Clock (GHz) Link Clock (MHz) Result
1 1 1 8 1 0 16 6.25 2.5 156.25 PASS
2 1 1 8 1 1 16 6.25 2.5 156.25 PASS
3 1 1 8 1 0 32 6.25 2.5 156.25 PASS
4 1 1 8 1 1 32 6.25 2.5 156.25 PASS
5 2 1 4 1 0 16 6.25 2.5 156.25 PASS
6 2 1 4 1 1 16 6.25 2.5 156.25 PASS
7 2 1 4 1 0 32 6.25 2.5 156.25 PASS
8 2 1 4 1 1 32 6.25 2.5 156.25 PASS
9 4 1 2 1 0 16 6.25 2.5 156.25 PASS
10 4 1 2 1 1 16 6.25 2.5 156.25 PASS
11 4 1 2 1 0 32 6.25 2.5 156.25 PASS
12 4 1 2 1 1 32 6.25 2.5 156.25 PASS
13 6 1 1 1 0 20 6.25 2.5 156.25 PASS with comments
14 6 1 1 1 1 20 6.25 2.5 156.25 PASS with comments
15 6 1 1 1 0 32 6.25 2.5 156.25 PASS with comments
16 6 1 1 1 1 32 6.25 2.5 156.25 PASS with comments
17 8 1 1 1 0 20 6.25 2.5 156.25 PASS
18 8 1 1 1 1 20 6.25 2.5 156.25 PASS
19 8 1 1 1 0 32 6.25 2.5 156.25 PASS
20 8 1 1 1 1 32 6.25 2.5 156.25 PASS

The following table lists the results for test cases DL.1, DL.2, DL.3 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies

Table 12.  Results for Deterministic Latency Test (Arria 10 GX FPGA)
Test L M F Subclass K Data Rate (Gbps) Sampling Clock (GHz) Link Clock (MHz) Result
DL.1 1 1 8 1 32 6.25 2.5 156.25 PASS
DL.2 1 1 8 1 32 6.25 2.5 156.25 PASS
DL.3 1 1 8 1 32 6.25 2.5 156.25

PASS with comments.

Link clock observed = 319 with RBD offset register set to 5.

DL.1 2 1 4 1 32 6.25 2.5 156.25 PASS
DL.2 2 1 4 1 32 6.25 2.5 156.25 PASS
DL.3 2 1 4 1 32 6.25 2.5 156.25

PASS with comments.

Link clock observed = 187 with RBD offset register set to 9.

DL.1 4 1 2 1 32 6.25 2.5 156.25 PASS
DL.2 4 1 2 1 32 6.25 2.5 156.25 PASS
DL.3 4 1 2 1 32 6.25 2.5 156.25

PASS with comments.

Link clock observed = 99 with ADC LMFC offset register set to 0.

DL.1 6 1 1 1 32 6.25 2.5 156.25 PASS
DL.2 6 1 1 1 32 6.25 2.5 156.25 PASS
DL.3 6 1 1 1 32 6.25 2.5 156.25

PASS with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0.

DL.1 8 1 1 1 32 6.25 2.5 156.25 PASS
DL.2 8 1 1 1 32 6.25 2.5 156.25 PASS
DL.3 8 1 1 1 32 6.25 2.5 156.25

PASS with comments.

Link clock observed = 67 with ADC LMFC offset register set to 0.

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 10.  Deterministic Latency Measurement Ramp Test Pattern Diagram (Arria 10 GX FPGA)
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