AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

ID 683294
Date 6/13/2016

1.4.2. Receiver Transport Layer

The ADC is configured to output ramp or PRBS-23 test data pattern to check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer. The ADC is also set to operate with the same configuration as in the JESD204B IP core. The ramp or PRBS checker in the FPGA fabric checks the data integrity for one minute.

Figure 5.  Data Integrity Check Using Ramp or PRBS CheckerThis figure shows the conceptual test setup for data integrity checking.

The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3.  Transport Layer Test Case

Test Case



Passing Criteria


Check the transport layer mapping using ramp test pattern or PRBS-23 test pattern.

The following signal in are tapped:

  • jesd204_rx_data_valid

The following signals in are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the SignalTap II sampling clock.

The data_error signal indicates a pass or fail for the ramp checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

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