AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report
ID
683294
Date
6/13/2016
Public
1.1. Hardware Requirements
1.2. Hardware Setup for Stratix V Advanced Systems Development Kit
1.3. Hardware Setup for Arria 10 GX FPGA Development Kit
1.4. Hardware Checkout Methodology
1.5. JESD204B IP Core and AD9625 Configurations
1.6. Test Results
1.7. Test Result Comments
1.8. AN 712 Document Revision History
1.4.3. Descrambling
The ramp or PRBS checker at the RX transport layer checks the data integrity of the descrambler. The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
SCR.1 |
Check the functionality of the descrambler using ramp test or PRBS-23 test pattern. |
Enable scrambler at the ADC and descrambler at the RX JESD204B IP core. The signals that are tapped in this test case are similar to test case TL.1 |
|