AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report
ID
683294
Date
6/13/2016
Public
1.1. Hardware Requirements
1.2. Hardware Setup for Stratix V Advanced Systems Development Kit
1.3. Hardware Setup for Arria 10 GX FPGA Development Kit
1.4. Hardware Checkout Methodology
1.5. JESD204B IP Core and AD9625 Configurations
1.6. Test Results
1.7. Test Result Comments
1.8. AN 712 Document Revision History
1.4.1. Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization.
On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool monitors the receiver data link layer operation.