AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

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ID 683294
Date 6/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 GX FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and AD9625 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 712 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

1.8. AN 712 Document Revision History

Date Version Changes
June 2016 2016.06.13
  • Added Arria 10 FPGA hardware setup and test results.
  • Updated the Deterministic Latency Measurement Ramp Test Pattern Diagram for Stratix V FPGA.
  • Split the test results section to Stratix V and Arria 10 GX FPGA.
October 2014 2014.10.13 Initial release.
Level Two Title