Viterbi IP Core User Guide

ID 683280
Date 11/06/2017
Document Table of Contents

3.5.7. Viterbi IP Core Timing Diagrams

Figure 16. Hybrid Decoder Input Timing Diagram The sink_rdy signal is asserted for one clock cycle in every Z clock cycles. If the decoder becomes full because data is not being collected on the source side, it may deassert sink_rdy until it can accept new data. The decoder only accepts data, if sink_rdy is asserted.
Figure 17. Parallel Decoder Input Timing Diagram
Figure 18. Output Timing - Example 1The source_val signal is asserted initially for 8 or 16 clock cycles. It is then asserted for the number of clock cycles corresponding to the amount of remaining data, if source_rdy remains asserted. The typical ending of a block or packet in the Avalon-ST interface is on the source (Viterbi) to the sink (user) side connection.
Figure 19. Output Timing - Example 2With a different ending.
Figure 20. Depuncturing Timing DiagramThis depuncturing timing diagram shows eras_sym for the pattern 110110 (puncturing rate 3/4). By changing the eras_sym pattern you can implement virtually any depuncturing pattern you require.