Viterbi IP Core User Guide

ID 683280
Date 11/06/2017
Public
Document Table of Contents
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1.2. Viterbi IP Core Features

  • High-speed parallel architecture:
    • Performance of over 250 megabits per second (Mbps)
    • Fully parallel operation
    • Optimized block decoding and continuous decoding
  • Low to medium-speed, hybrid architecture:
    • Configurable number of add compare and select (ACS) units
    • Memory-based architecture
    • Wide range of performance; wide range of logic area
  • Fully parameterized Viterbi decoder, including:
    • Number of coded bits
    • Constraint length
    • Number of soft bits
    • Traceback length
    • Polynomial for each coded bit
  • Variable constraint length
  • Trellis coded modulation (TCM) option